Post-silicon Resource Binding Customization for Low Power

In this paper, we propose the first method for post-silicon customization of resource binding for low power application specific integrated circuits (ASICs) design. We devise and implement a new synthesis framework that generates a diverse set of resource binding candidates where any one of the candidates could be selected post-silicon. Orthogonal arrays are used to construct multiple candidates with diversified resource usage patterns. We tune the resource usage to match the unique power characteristic of each IC by selecting the best binding candidate that minimizes the pertinent chip’s power consumption. We show efficient methods for embedding multiple binding candidates inside one design. Experimental evaluations on benchmark circuits demonstrate the effectiveness and low overhead of the proposed methods. For example, our post-silicon tuning achieves an average of 10% power savings on the benchmark circuits for variations present in 45nm technology. The power savings of post-silicon binding customization are expected to increase with scaling and miniaturization of CMOS feature sizes that inherently incur higher variations.